1. Field of the Invention
The invention relates to a fabrication process of self-aligned metal silicide (salicide). More particularly, the invention relates to a method of fabricating salicide of a self-aligned contact without causing the problems such of bridge effect and junction leakage.
2. Description of the Related Art
As the integrated circuits have been continuously developed to achieve a higher integration, the linewidth, contact area, and junction depth of the integrated circuits or the devices thereon have to be scaled down. To effectively enhance the performance of devices, the resistance is reduced to minimize signal transmission delay caused by the resistance and capacitance. It is therefore a trend for fabricating a metal sicilide at a junction to reduce the contact resistance. However, many structures or patterns are formed by only one step of photolithography, therefore, the alignment tolerance of photolithography thus becomes smaller for the smaller devices. Consequently, a fabrication process with a self-aligned effect such as fabrication process for forming a self-aligned metal silicide layer and self-aligned contact window becomes more and more important.
Between two neighboring spacers of two neighboring gates, a self-aligned contact window is formed under the conditions of a large selectivity between the spacers and an insulation layer, and the formation of cap layers to protect the gates. With the cap layers, the alignment window for photolithography is widened, and the gates are protected from being damaged while etching the insulation layer. On the other hand, a MOS transistor is formed in advance when a self-aligned contact window is formed to expose a gate of the MOS transistor. A metal is sputtered onto the MOS transistor which has been formed in advance, followed by reacting into a metal silicide layer. The cap layers on the gates thus encumber the reaction of the metal layer, and therefore, inhibits the formation of the metal silicide layer. Though the gates may also be made of material with a low resistivity such as polycide, taking tungsten silicide as an example, the junction resistance between the polycide and the polysilicon of the gate is as high as 10 .OMEGA., which can not meet the requirement of a sub-micron technology. In addition, when the gates are implanted with doping material to adjust the conduction type of gate, doping material can not penetrate through the silicide layer. Therefore, it is more difficult to achieve the requirement of surface channel device for sub-quarter micron technology.
Titanium silicide (TiSi.sub.2) is a material widely applied to form the metal silicide layer on the MOS transistor due to the low resistivity. In the thermal process for forming the titanium silicide layer, silicon is the moving species with a better mobility as the temperature raises. Moreover, the temperature for forming the titanium silicide layer can not be lower than 600.degree. C. Thus, a great amount of the silicon atoms diffuses onto a surface of the spacer and reacts with the titanium to form titanium silicide on the spacer, a bridging effect is thus caused. More seriously, a short circuit may even occur between the gate and the source/drain region.
Another drawback of the titanium silicide formed by a conventional method is a narrow linewidth effect. That is, when the linewidth is under 0.25 .mu.m, the sheet resistance is obviously increased as the reduction of gate linewidth. This is because the number of nucleation sites for transforming the high-resistance C-49 phase of titanium silicide into a low-resistance C-54 phase is limited. Typically, before sputtering the metal, a pre-amorphous implantation is performed to increase the nucleation sites. However, if conditions of the pre-amorphous implantation are not well controlled, plus silicon atoms tend to move towards to titanium during the formation of the titanium silicide, voids are formed in the source/drain region, and a junction leakage is evoked.